Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.3.1. Stratix 10 HPS Master Caching and Buffering Overrides

Some of the peripheral masters connected to the System Interconnect do not have the ability to drive the caching and buffering signals of their interfaces. The system manager provides registers so that you can enable cacheable and bufferable transactions for these masters.

Table 60.  Transaction Attribute Source: Pre-TBU AHB Masters
AHB Bus Signals AHB Masters (Pre-TBU)
SDMMC USB0 USB1
HPROT[3:0] Sys Mgr8 Sys Mgr Sys Mgr
HAUSER[0]: Allocate Sys Mgr Sys Mgr Sys Mgr
HAUSER[1]: Secure Sys Mgr Sys Mgr Sys Mgr
HAUSER[5:2]: Snoop 3'b000 3'b000 3'b000
HAUSER[7:6]: Domain Sys Mgr Sys Mgr Sys Mgr
HAUSER[9:8]: Bar 2'b00 2'b00 2'b00
*_ns A*PROT[1] A*PROT[1] A*PROT[1]
HAUSER[22:13]: xsid Sys Mgr Sys Mgr Sys Mgr
HAUSER[12:10]: USER ID 3'b010 3'b011 3'b100
Table 61.  Transaction Attribute Source: Pre-TBU AXI Masters
AXI Bus Signals AXI Masters (Pre-TBU)
EMAC0 EMAC1 EMAC2 NAND DMAC ETR SDM2HPS BE
AxSNOOP 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000
AxDOMAIN Sys Mgr Sys Mgr Sys Mgr Sys Mgr Sys Mgr Sys Mgr Sec Mgr
AxBAR 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
ARCACHE Sys Mgr Sys Mgr Sys Mgr Sys Mgr DMAC ETR Sec Mgr
AWCACHE Sys Mgr Sys Mgr Sys Mgr Sys Mgr DMAC ETR Sec Mgr
AxPROT Sys Mgr Sys Mgr Sys Mgr Sys Mgr DMAC ETR SDM
*_ns A*PROT[1] A*PROT[1] A*PROT[1] A*PROT[1] A*PROT[1] A*PROT[1] A*PROT[1]
AxUSER[12:3]: xsid Sys Mgr Sys Mgr Sys Mgr Sys Mgr

Sys Mgr[9:4],

A*ID[3:0]

Sys Mgr Sec Mgr
AxUSER[2:0]: USER ID 3'b000 3'b001 3'b010 3'b000 3'b000 3'b101 USER[2:0]
Table 62.  Transaction Attribute Source: Post-TBU AXI Masters
AXI Bus Signals AXI Masters (post-TBU)
EMAC_TBU DMA_TBU IO_TBU SDM_TBU
AxSNOOP TBU TBU TBU TBU
AxDOMAIN TBU TBU TBU TBU
AxBAR TBU TBU TBU TBU
ARCACHE TBU TBU TBU TBU
AWCACHE TBU TBU TBU TBU
AxPROT TBU TBU TBU TBU
*_ns n/a n/a n/a n/a
xsid n/a n/a n/a n/a
AxUSER[7:0]: USER ID 5'b10100, USER[2:0] 5'b10000, USER[2:0] 5'b11100, USER[2:0] 5'b00110, USER[2:0]
Table 63.  Transaction Attribute Source: AXI Masters (No TBU)
AXI Bus Signals AXI Masters (no TBU)
SDM2HPS LL FPGA2SDRAM0 FPGA2SDRAM1 FPGA2SDRAM2 AXI-AP
AxSNOOP 3'b000 FPGA FPGA FPGA AXI-AP
AxDOMAIN Sec Mgr FPGA FPGA FPGA AXI-AP
AxBAR 2'b00 FPGA FPGA FPGA AXI-AP
ARCACHE Sec Mgr FPGA FPGA FPGA AXI-AP
AWCACHE Sec Mgr FPGA FPGA FPGA AXI-AP
AxPROT SDM FPGA FPGA FPGA AXI-AP
*_ns n/a n/a n/a n/a n/a
xsid n/a n/a n/a n/a n/a
AxUSER[7:0]: USER ID 5'b00100, USER[2:0] 8'b11100000 8'b11100001 8'b11100010 8'b01100000

At reset time, some of the masters in the tables above do not provide their own cache and buffering signals. For these masters, at reset time, the system manager drives the cache and buffering signals low. In other words, these masters do not support cacheable or bufferable accesses until you enable them after reset. There is no synchronization between the system manager and the system interconnect, so avoid changing these settings when any of the masters are active.

8 Sys Mgr: System Manager