Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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25.4.13. Debug Clocks

The CoreSight system monitors four clocks from clock manager.
Table 222.  CoreSight Clocks

Port Name

Clock Source

Signal Name

Description

ATCLK

Clock manager

cs_at_clk

Trace bus clock.

CTICLK (for CTI)

Clock manager

cs_at_clk

Cross trigger interface clock for CTI. It can be synchronous or asynchronous to CTMCLK.

CTICLK (for FPGA–CTI)

FPGA fabric

cs_at_clk

There are multiple CTIs, each with a different clock. The FPGA–CTI clock comes from the CS subsystem.

CTMCLK

Clock manager

cs_pdbg_clk

Cross trigger matrix clock. It can be synchronous or asynchronous to CTICLK.

DAPCLK

Clock manager

cs_pdbg_clk

DAP internal clock. It must be equivalent to PCLKDBG.

PCLKDBG

Clock manager

cs_pdbg_clk

Debug APB (DAPB) clock.

PCLKSYS

Clock manager

cs_pdbg_clk

Used by the APB slave port inside the DAP. It is asynchronous to DAPCLK; and is the same as the tck signal from JTAG.

SWCLKTCK

JTAG interface

dap_tck

This is the SWJ-DP clock driven by the external debugger and is synchronous to DAPCLK. This clock is the same as the tck signal from JTAG.

TRACECLKIN

(from the SoC)

Clock manager

cs_trace_clk

TPIU trace clock input. It is asynchronous to ATCLK. In the HPS, this clock comes from the clock manager.

FPGA fabric

tpiu_traceclkin

TPIU trace clock input. It is asynchronous to ATCLK. In the HPS, this clock comes from the FPGA fabric.

For more information about the CoreSight port names, refer to the CoreSight Technology System Design Guide on the ARM® Infocenter website.