Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.6.2. HPS-to-FPGA Bridge Clocks and Resets

The master interface into the FPGA fabric operates in the hps2fpga_clk clock domain. The slave interface of the bridge in the HPS logic operates in the l3_main_clk clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS.

The HPS-to-FPGA bridge has one reset signal, hps2fpga_bridge_rst_n . The reset manager asserts this signal to the HPS-to-FPGA bridge on a cold or warm reset.