Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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16.3. SD/MMC Controller Signal Description

The following table shows the SD/MMC controller signals that are connected to the FPGA and the HPS I/O.

Table 126.  SD/MMC Controller Interface Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
SDMMC_CCLK 1 Output Clock from controller to the card
SDMMC_CMD 1 Input / Output Card command Pull-up
SDMMC_D[7:0] 8 Input / Output Card data Pull-up
SDMMC_PWR_ENA 1 Output External device power enable
Table 127.  SD/MMC Controller Interface Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
sdmmc_cclk_out 1 Output Clock from controller to the card
sdmmc_cmd_i 1 Input Card command 1'b1 Pull-up
sdmmc_cmd_o 1 Output Card command
sdmmc_cmd_oe 1 Output Card command
sdmmc_data_i [7:0] 8 Input Card data 8'b11111111 Pull-up
sdmmc_data_o [7:0] 8 Output Card data
sdmmc_data_oe [7:0] 8 Output Card data
sdmmc_pwr_ena_o 1 Output External device power enable
sdmmc_cdn_i 1 Input Card detect signal - active low 1'b0 Pull-down
sdmmc_wp_i 1 Input Card write protect signal - active high 1'b0 Pull-down
sdmmc_vs_o 1 Output Voltage switching between 3.3 V and 1.8 V
sdmmc_rstn_o 1 Output Card reset signal used in MMC mode
sdmmc_card_intn_i 1 Input Card interrupt signals - active low 1'b1 Pull-up
sdmmc_intr 1 Output Interrupt