Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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16.4.2.2. Register Block

The register block is part of the BIU and provides read and write access to the CSRs.

All registers reside in the BIU clock domain, l4_mp_clk. When a command is sent to a card by setting the start command bit (start_cmd) of the command register (cmd) to 1, all relevant registers needed for the CIU operation are copied to the CIU block. During this time, software must not write to the registers that are transferred from the BIU to the CIU. The software must wait for the hardware to reset the start_cmd bit to 0 before writing to these registers again. The register unit has a hardware locking feature to prevent illegal writes to registers.