Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

B.6.1. Setting Up the Quad SPI Flash Controller

The following steps describe how to set up the quad SPI controller:

  1. Wait until any pending operation has completed.
  2. Disable the quad SPI controller with the quad SPI enable field (en) of the cfg register.
  3. Update the instwidth field of the devrd register with the instruction type you wish to use for indirect and direct writes and reads.
  4. If mode bit enable bit (enmodebits) of the devrd register is enabled, update the mode bit register (modebit).
  5. Update the devsz register as needed.
    Parts or all of this register might have been updated after initialization. The number of address bytes is a key configuration setting required for performing reads and writes. The number of bytes per page is required for performing any write. The number of bytes per device block is only required if the write protect feature is used.
  6. Update the device delay register (delay).
    This register allows the user to adjust how the chip select is driven after each flash access. Each device may have different timing requirements. If the serial clock frequency is increased, these timing requirements become more critical. The numbers specified in this register are based on the period of the qspi_ref_clk clock. For example, some devices need 50 ns minimum time before the slave select can be reasserted after it has been deasserted. When the device is operating at 100 MHz, the clock period is 10 ns, so 40 ns extra is required. If the qspi_ref_clk clock is running at 400 MHz (2.5 ns period), specify a value of at least 16 to the clock delay for chip select deassert field (nss) of the delay register.
  7. Update the remapaddr register as needed.
    This register only affects direct access mode.
  8. Set up and enable the write protection registers (wrprot, lowwrprot, and uppwrprot) when write protection is required.
  9. Enable required interrupts through the irqmask register.
  10. Set up the bauddiv field of the cfg register to define the required clock frequency of the target device.
  11. Update the read data capture register (rddatacap) if you need to change the auto-filled value.

    This register delays when the read data is captured and can help when the read data path from the device to the quad SPI controller is long and the device clock frequency is high.

  12. Enable the quad SPI controller with the en field of the cfg register.