Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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11.3.5. Software Sequenced Clocks

The software sequenced clock groups include additional clocks for peripherals not covered by the MPU and NOC clocks. The main purpose is to have a second PLL for the Ethernet 250 MHz clock reference. The following diagram shows the external bypass muxes, hardware-managed external counters and dividers, and clock gates.

Figure 42. Peripheral Clocks

There are 3 EMAC cores that have a very strict requirement of either a 250 MHz or 50 MHz clock reference. If the PLL0 frequency is a multiple of 250 MHz (for example 1.5 GHz), driving the EMAC clocks from PLL0 provides PLL1 with more flexibility in VCO clock frequency. In addition, to minimize the PLL clock outputs required, emac_clka can be 250 MHz and emac_clkb can be 50 MHz, allowing each EMAC core to be software configured to select 250 MHz or 50 MHz.

Table 99.  Software Sequenced Clocks Feature Summary
System Clock Name Frequency Boot Frequency Descriptions
emac{0,1,2}_clk PLL C2 or PLL C3 boot_clk Clock for EMAC. Fixed at 250 MHz or 250 MHz emac_clk and 50 MHz emacb_clk
emac_ptp_clk PLL C4 boot_clk Clock for EMAC PTP timestamp clock
gpio_db_clk 125 Hz to PLL C5 boot_clk Clock for GPIO debounce clock
sdmmc_clk PLL C6 boot_clk Clock for SDMMC
h2f_user0_clk PLL C7 boot_clk Clock reference for FPGA
h2f_user1_clk PLL C8 boot_clk Clock reference for FPGA