Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.5.10. ACE Bus Interface

The ACE bus interface operates in the mpu_ccu_clk domain, which is mpu_clk/2. This bus provides an AXI3 compatibility mode with support for privilege level accesses through the ARPROTM[0] and AWPROTM[0] signals.

The Cortex® -A53 MPCore™ processor does not generate any FIXED bursts and all WRAP bursts fetch a complete cache line starting with the critical word first. A burst does not cross a cache line boundary. The cache linefill fetch length is always 64 bytes. The Cortex® -A53 generates only a subset of all possible AXI transactions on the master interface.

For WriteBack transfers the supported transfers are:

  • WRAP 4 128-bit for read transfers (linefills).
  • INCR 4 128-bit for write transfers (evictions).
  • INCR N (N:1, 2, or 4) 128-bit write transfers (read allocate).

For non-cacheable transactions:

  • INCR N (N:1, 2, or 4) 128-bit for write transfers.
  • INCR N (N:1, 2, or 4) 128-bit for read transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for read transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for write transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for exclusive write transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for exclusive read transfers.

For Device transactions:

  • INCR N (N:1, 2, or 4) 128-bit read transfers.
  • INCR N (N:1, 2, or 4) 128-bit write transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit read transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit write transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit exclusive read transfers.
  • INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit exclusive write transfers.

For translation table walk transactions INCR 1 32-bit, and 64-bit read transfers.

The following characteristics apply to AXI transactions:

  • WRAP bursts are only 128-bit.
  • INCR 1 can be any size for read or write.
  • INCR burst, more than one transfer, are only 128-bit.
  • No transaction is marked as FIXED.
  • Write transfers with all, some or no byte strobes HIGH can occur.