Intel® Stratix® 10 Hard Processor System Technical Reference Manual
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6.2. Functional Description of the Stratix 10 HPS System Interconnect
The system interconnect, in conjunction with the system MMU (SMMU), provides access to a 132-GB address space.
Address spaces are divided into one or more regions.
The following figure shows the relationships between the HPS address spaces. The figure is not to scale.
The table below shows the HPS address spaces and the masters that access those address spaces.
Name | Size | Type (Physical/Virtual) | Masters |
---|---|---|---|
MPU view of the HPS/MPU address map | 132 GB | P/V | MPU and FPGA-to-HPS bridge |
L3 NoC view of the HPS/MPU address map | 4 GB 6 | P | All L3 masters |
132 GB | V | All L3 masters, with SMMU enabled | |
FPGA Slaves region of the HPS/MPU address map | 4 GB | P | All masters accessing the HPS-to-FPGA bridge |
Lightweight FPGA Slave region of the HPS/MPU address map | 2 MB | P | All masters accessing the lightweight HPS-to-FPGA bridge |
FPGA to SDRAM Interface view of the DDR address map | 128 GB | P | FPGA masters accessing HPS SDRAM through the FPGA-to-SDRAM interfaces |
Section Content
Stratix 10 System Interconnect Address Spaces
Secure Transaction Protection
Stratix 10 HPS System Interconnect Master Properties
Stratix 10 HPS System Interconnect Slave Properties
System Interconnect Clocks
Stratix 10 HPS System Interconnect Resets
Functional Description of the Rate Adapters
Functional Description of the Firewalls
Functional Description of the SDRAM L3 Interconnect
Functional Description of the Arbitration Logic
Functional Description of the Observation Network