Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.8.3.4. Layer 3 and Layer 4 Filters Register Set

The MAC implements a set of registers for Layer 3 and Layer 4 based frame filtering. In this register set, there is a control register for frame filtering and five address registers.

You can configure the MAC to have up to four such independent set of registers.

The registers available for programming are as follows:

  • gmacgrp_l3_l4_control0 through gmacgrp_l3_l4_control3 registers: Layer 3 and Layer 4 Control registers
  • gmacgrp_layer4_address0 through gmacgrp_layer4_address3 registers: Layer 4 Address registers
  • gmacgrp_layer3_addr0_reg0 through gmacgrp_layer3_addr0_reg3 registers: Layer 3 Address 0 registers
  • gmacgrp_layer3_addr1_reg0 through gmacgrp_layer3_addr1_reg3 registers: Layer 3 Address 1 registers
  • gmacgrp_layer3_addr2_reg0 through gmacgrp_layer3_addr2_reg3 registers: Layer 3 Address 2 registers
  • gmacgrp_layer3_addr3_reg0 through gmacgrp_layer3_addr3_reg3 registers: Layer 3 Address 3 registers