Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3. CCU Connectivity

The Cortex® -A53 MPCore™ , FPGA-to-HPS bridge, TCU and peripheral masters are connected coherently to memory and slave agents through the coherency interconnect.

The CCU supports communication between different protocols by packetizing accesses into a common protocol, routing an access to a specific port and depacketizing the transaction before it reaches the slave agent. Not all master agents have access to all five slave agents interfacing to the CCU.
Table 40.  CCU ConnectivityAn "X" in the table indicates that the slave agent is connected to the master agent through the coherency interconnect. A blank entry indicates that there is no connection between the slave and master agent.
Slave Agents Master Agents
Cortex® -A53 MPCore™ FPGA-to-HPS Bridge

Peripherals

(EMACs, USB, DMA, NAND, SDMMC, ETR)

Translation Control Unit (TCU)
External SDRAM memory X X X X
On-chip RAM X X X X
Peripheral slaves X X X X
SDRAM registers X X X  
Generic Interrupt Controller X   X  
Note: The Cortex® -A53 MPCore™ also has access to the CCU Control and Status Registers (CSRs).