Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

20.1. Features of the I2C Controller

The I2C controller has the following features:

  • Maximum clock speed of up to 400 Kbps
  • Standard clock speed 100 kbps
  • One of the following I2C operations:
    • A master in an I2C system and programmed only as a master †
    • A slave in an I2C system and programmed only as a slave †
  • 7- or 10-bit addressing †
  • Mixed read and write combined-format transactions in both 7-bit and 10-bit addressing mode †
  • Bulk transmit mode †
  • Transmit and receive buffers †
  • Handles bit and byte waiting at all bus speeds †
  • DMA handshaking interface †
Three of the five I2Cs, provide support for EMAC communication. They provide flexibility for the EMACs to use MDIO or I2C for PHY communication and can also be used as general purpose.
  • I2C_EMAC0
  • I2C_EMAC1
  • I2C_EMAC2
The remaining two I2Cs are intended for general purpose.
  • I2C0
  • I2C1