Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.5.8. Cache Coherency Unit Reset

The CCU is reset on a cold reset.
On a CCU reset, the CCU coherency directory and all ECC bits are cleared. During HPS boot, the first-stage boot loader must enable CPU0 and I/O master access to DDR through the CCU by clearing the DI bit in the following registers:
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ddrreg_sprt_ddrregspace0_0
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace0a_0
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace0b_0
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1a_0
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1c_0
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1d_0
  • bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1e_0
  • bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace0a_0
  • bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1a_0
  • bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1b_0
  • bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1c_0
  • bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1d_0
  • bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1e_0