Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

4.1. Supported Features

  • Coherency directory to track the state of the 1 MB L1 and L2 cache in the ARM® Cortex® -A53 MPCore™
  • Snoop filter support
  • Speculative fetch support for lower latency accesses
  • Single-bit error correction and double-bit error detection (SECDED) in the coherency directory
  • Support for distributed virtual memory (DVM) using the ARM® Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) Coherency Extensions, also known as the ACE protocol. The CCU sends distributed virtual memory broadcast messages to the Cortex® -A53 MPCore™ and the TCU in the SMMU.
  • Quality of service (QoS) support for transaction prioritization using a weight bandwidth allocation
  • Flexible address range programming for each master-to-slave connection
  • Interconnect debug capability through master and slave bridge status registers
  • Interrupt support for CCU transaction and counter events