Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.4. IEEE 1588-2002 Timestamps

The IEEE 1588‑2002 standard defines the Precision Time Protocol (PTP) that enables precise synchronization of clocks in a distributed network of devices. The PTP applies to systems communicating by local area networks supporting multicast messaging. This protocol enables heterogeneous systems that include clocks of varying inherent precision, resolution, and stability to synchronize. It is frequently used in automation systems where a collection of communicating machines such as robots must be synchronized and hence operate over a common time base. 49

The PTP is transported over UDP/IP. The system or network is classified into Master and Slave nodes for distributing the timing and clock information.

The following figure shows the process that PTP uses for synchronizing a slave node to a master node by exchanging PTP messages.

Figure 86. Networked Time Synchronization

 The PTP uses the following process for synchronizing a slave node to a master node by exchanging the PTP messages:

  1. The master broadcasts the PTP Sync messages to all its nodes. The Sync message contains the master’s reference time information. The time at which this message leaves the master’s system is t1. This time must be captured, for Ethernet ports, at the PHY interface.
  2. The slave receives the sync message and also captures the exact time, t2, using its timing reference.
  3. The master sends a follow_up message to the slave, which contains t1 information for later use.
  4. The slave sends a delay_req message to the master, noting the exact time, t3, at which this frame leaves the PHY interface.
  5. The master receives the message, capturing the exact time, t4, at which it enters its system.
  6. The master sends the t4 information to the slave in the delay_resp message.
  7. The slave uses the four values of t1, t2, t3, and t4 to synchronize its local timing reference to the master’s timing reference.

Most of the PTP implementation is done in the software above the UDP layer. However, the hardware support is required to capture the exact time when specific PTP packets enter or leave the Ethernet port at the PHY interface. This timing information must be captured and returned to the software for the proper implementation of PTP with high accuracy.

The EMAC is intended to support IEEE 1588 operation in all modes with a resolution of 10 ns. When the three EMACs are operating in an IEEE 1588 environment, the Cortex-A53 MPCore processor is responsible for maintaining synchronization between the time counters internal to the three MACs.

The IEEE 1588 interface to the FPGA allows the FPGA to provide a source for the emac_ptp_ref_clk input as well to allow it to monitor the pulse per second output from each EMAC controller.

The EMAC component provides a hardware assisted implementation of the IEEE 1588 protocol. Hardware support is for timestamp maintenance. Timestamps are updated when receiving any frame on the PHY interface, and the receive descriptor is updated with this value. Timestamps are also updated when the SFD of a frame is transmitted and the transmit descriptor is updated accordingly.

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