Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

20.4.3.2.2. 10-Bit Address Format

During 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte contains the following bit definition. The first five bits (bits 7:3) notify the slaves that this is a 10-bit transfer followed by the next two bits (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (bit 0) is the R/W bit. The second byte transferred sets bits 7:0 of the slave address. †

Figure 115. 10-Bit Address Format

The following table defines the special purpose and reserved first byte addresses. †

Table 204.  I2C Definition of Bits in First Byte

Slave Address

R/W Bit

Description

0000 000

0

General call address. The I2C controller places the data in the receive buffer and issues a general call interrupt.

0000 000

1

START byte. For more details, refer to “START BYTE Transfer Protocol”

0000 001

X

CBUS address. The I2C controller ignores these accesses.

0000 010

X

Reserved

0000 011

X

Reserved

0000 1XX

X

Unused

1111 1XX

X

Reserved

1111 0XX

X

10-bit slave addressing.

Note to Table: ‘X’ indicates do not care.