Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.4.2. System Time Register Module

The 64‑bit time is maintained in this module and updated using the input reference clock, clk_ptp_ref, which can be the emac_ptp_clk from the HPS or the f2h_ptp_ref_clk from the FPGA. The emac_ptp_clk in the HPS is a derivative of the osc1_clk and is configured in the clock manager. This input reference clock is the source for taking snapshots (timestamps) of Ethernet frames being transmitted or received at the PHY interface.

The system time counter can be initialized or corrected using the coarse correction method. In this method, the initial value or the offset value is written to the Timestamp Update register. For initialization, each EMAC system time counter is written with the value in the Timestamp Update registers, while for system time correction, the offset value is added to or subtracted from the system time.

With the fine correction method, a slave clock’s frequency drift with respect to the master clock is corrected over a period of time instead of in one clock, as in coarse correction. This protocol helps maintain linear time and does not introduce drastic changes (or a large jitter) in the reference time between PTP sync message intervals.

With this method, an accumulator sums up the contents of the Timestamp_Addend register, as shown in the figure below. The arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter. The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high-precision frequency multiplier or divider.

Note: You must connect a PTP clock with a frequency higher than the frequency required for the specified accuracy.
Figure 87. Algorithm for System Time Update Using Fine Method

The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns accuracy. The frequency division ratio (FreqDivisionRatio) is the ratio of the reference clock frequency to the required clock frequency. Hence, if the reference clock (clk_ptp_ref_i) is for example, 66 MHz, this ratio is calculated as 66 MHz / 50 MHz = 1.32. Hence, the default addend value to program in the register is 232 / 1.32, 0xC1F07C1F.

If the reference clock drifts lower, to 65 MHz for example, the ratio is 65 / 50, or 1.3 and the value to set in the addend register is 232 / 1.30, or 0xC4EC4EC4. If the clock drifts higher, to 67 MHz for example, the addend register must be set to 0xBF0B7672. When the clock drift is nil, the default addend value of 0xC1F07C1F (232 / 1.32) must be programmed.

In the above figure, the constant value used to accumulate the sub-second register is decimal 43, which achieves an accuracy of 20 ns in the system time (in other words, it is incremented in 20-ns steps).

The software must calculate the drift in frequency based on the Sync messages and update the Addend register accordingly.

Initially, the slave clock is set with FreqCompensationValue0 in the Addend register. This value is as follows:
FreqCompensationValue0 = 232 / FreqDivisionRatio

If MasterToSlaveDelay is initially assumed to be the same for consecutive sync messages, the algorithm described below must be applied. After a few sync cycles, frequency lock occurs. The slave clock can then determine a precise MasterToSlaveDelay value and re-synchronize with the master using the new value.

The algorithm is as follows:

  • At time MasterSyncTimen the master sends the slave clock a sync message. The slave receives this message when its local clock is SlaveClockTimen and computes MasterClockTimen as:
    MasterClockTimen = MasterSyncTimen + MasterToSlaveDelayn
  • The master clock count for current sync cycle, MasterClockCountn is given by:
    MasterClockCountn = MasterClockTimen – MasterClockTimen-1

    (assuming that MasterToSlaveDelay is the same for sync cycles n and n – 1)

  • The slave clock count for current sync cycle, SlaveClockCountn is given by:
    SlaveClockCountn = SlaveClockTimen – SlaveClockTimen-1
  • The difference between master and slave clock counts for current sync cycle, ClockDiffCountn is given by:
    ClockDiffCountn = MasterClockCountn – SlaveClockCountn
  • The frequency-scaling factor for the slave clock, FreqScaleFactorn is given by:
    FreqScaleFactorn = (MasterClockCountn + ClockDiffCountn) / SlaveClockCountn
  • The frequency compensation value for Addend register, FreqCompensationValuen is given by: 
    FreqCompensationValuen = FreqScaleFactorn × FreqCompensationValuen-1 – 1

In theory, this algorithm achieves lock in one Sync cycle; however, it may take several cycles, because of changing network propagation delays and operating conditions.

This algorithm is self-correcting: if for any reason the slave clock is initially set to a value from the master that is incorrect, the algorithm corrects it at the cost of more Sync cycles.