Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

1. Intel Stratix 10 Hard Processor System Technical Reference Manual Revision History

Updated for:
Intel® Quartus® Prime Design Suite 22.4
Table 1.   Intel Stratix 10 Hard Processor System Technical Reference Manual Revision History Summary
Chapter Date of Last Update
Introduction to the Hard Processor System August 22, 2022
Cortex*-A53 MPCore Processor September 19, 2023
Cache Coherency Unit November 6, 2017
System Memory Management Unit May 3, 2019
System Interconnect January 25, 2024
HPS-FPGA Bridges June 8, 2021
DMA Controller January 25, 2020
On-Chip RAM November 6, 2017
Error Checking and Correction Controller November 6, 2017
Clock Manager January 25, 2024
Reset Manager January 27, 2023
System Manager September 28, 2021
Hard Processor Subsystem I/O Pin Multiplexing July 17, 2023
NAND Flash Controller September 19, 2023
SD/MMC Controller January 11, 2024
Ethernet Media Access Controller January 25, 2023
USB 2.0 OTG Controller November 28, 2022
SPI Controller November 28, 2022
I2C Controller November 28, 2022
UART Controller November 28, 2022
General-Purpose I/O Interface November 28, 2022
Timer November 6, 2017
Watchdog Timer November 6, 2017
CoreSight* Debug and Trace May 7, 2018
Booting and Configuration March 9, 2021
Accessing the SDM Quad SPI Flash Controller through HPS June 18, 2018
Operational Status of the HPS to the FPGA Logic January 11, 2024
Table 2.  Introduction to the Hard Processor System Revision History

Document Version

Changes

2022.08.22 Made the following changes:
  • Removed RGMII because it does not support FPGA I/O
2018.08.08 Removed support for multi-master mode in SPI Master Controllers section.
2018.05.07 Added the "Accessing the Intel® Stratix® 10 HPS Component Reference Manual" section.
2017.11.06 Added S10 Address Map and Register Definitions to the "Introduction to the Hard Processor System Address Map" section.
2017.06.20 Corrected FPGA-to-SDRAM data width in "Features of the HPS", "HPS-FPGA Memory-Mapped Interfaces" and "Stratix 10 HPS SDRAM L3 Interconnect" sections. The corrected data width is 32, 64, or 128 bits; not fixed 128 bits
2017.05.08 Maintenance release
2016.10.28
  • The Cortex-A53 MPCore Processor and the SMMU topics have been updated
  • Updated Figure 2 to indicate width of interface between the CCU and OCRAM

2016.08.01

Initial release

Introduction to the Hard Processor System
Table 3.   Cortex*-A53 MPCore Processor Revision History

Document Version

Changes

2023.09.19 Made the following updates:
  • Updated the reset sequence for all cores in the Bringing the Cortex* -A53 MPCore out of Reset section.
2021.11.12 Corrected the numbering for the FPGA to HPS interrupt numbers in the GIC Interrupt Map table.
2018.05.07
  • Added Initializing Instruction and Data Caches section.
  • Added SDM mailbox, SDM Quad SPI and SDM SD/MMC interrupts to the GIC Interrupt Map for the Intel® Stratix® 10 SoC HPS section.
2017.11.06 Added address map and register description links for the Cortex*-A53 MPCore Processor in the Address Map and Register Descriptions section.
2017.05.08 Renamed " Arm* Cortex*-A53 Timers" section to "Generic Timers" and renamed "Global Timer" section to "System Counter." Content in each section was updated.
2016.10.28
  • Modified Cortex*-A53 MPCore System Integration diagram
  • Added the Virtualization section and Virtual Interrupts subsection
  • Modified GIC Block Diagram
  • Modified table in the GIC Interrupt Map for the Intel® Stratix® 10 SoC HPS section
2016.08.01 Initial release
Cortex-A53 MPCore Processor
Table 4.  Cache Coherency Unit Revision History
Document Version Changes
2017.11.06
  • Added Bridge Registers section
  • Added Cache Coherency Unit Traffic Management section and the subsections Quality of Service, Transmit Rate Limiters and Rate Limiter Configuration
  • Added information regarding CCU register configuration that is required to enable SDRAM out of reset in the Cache Coherency Unit Reset section
  • Added a note regarding SMMU TBU configuration for successful master coherent transactions in the Cache Coherency Unit Transactions section
  • Added Disabling the FPGA-to-HPS Interface to CCU section
  • Added Specifying Address Ranges for Slave Devices section
  • Added address map and register description links for the CCU in the Address Map and Register Descriptions section.
2017.05.08 Added the following sections in the Cache Coherency:
  • Cache Coherency Unit Transactions
  • Bridges
  • Cache Coherency Controller and its subsections
  • I/O Coherency Bridge
  • Distributed Virtual Memory
  • Cache Coherency Unit Clocks
  • Cache Coherency Unit Reset
  • Programming Guidelines and all of its subsections
2016.10.28 Enhanced Cache Coherency System Diagram
2016.08.01 Initial Release
Cache Coherency Unit
Table 5.  System Memory Management Unit Revision History

Document Version

Changes

2019.05.03 Corrected a broken link in the "System Memory Management Unit" section.
2017.11.06
  • Updated SMMU revision number to r2p4 in the System Memory Management Unit section
  • Added HPS Master Stream ID table in the Stream ID section
  • Added the following sections:
    • System Memory Management Unit Reset
    • System Memory Management Unit Clocks
    • System Memory Management Unit Configuration
  • Added address map and register description links for the SMMU in the Address Map and Register Descriptions section.
2017.05.08
  • Updated System Memory Management Unit Block Diagram with more detail
  • Added the following sections:
    • Security State Determination
    • Stream ID section
    • Quality of Service Arbitration section
2016.10.28 Added the following sections:
  • System Memory Management Unit Functional Description and subsections
  • System Memory Management Unit Interrupts section
2016.08.01 Initial release
System Memory Management Unit
Table 6.  System Interconnect Revision History

Document Version

Changes

2024.01.25 Revised the Example (Recommended) System Memory Mapping Scheme section to include the support for Clam Shell Mode. Added the memory map table using Clam Shell Mode.
2022.11.28 Updated the Example (Recommended) System Memory Mapping Scheme section
2022.08.22 Added new section: Example (Recommended) System Memory Mapping Scheme
2021.02.23 Changed the "self-refresh" information in SDRAM L3 Interconnect Resets
2020.01.25 Corrected the Peripheral Region Address Map.
2018.09.24
2018.05.07 Maintenance release
2017.11.06
  • Updated the following figures:
    • High-Level System Interconnect Block Diagram
    • SDRAM L3 Interconnect Block Diagram
    • HPS Address Space Relationships
  • Added new figures:
    • HPS I/O Masters
    • HPS L4 Peripheral Bus Group
    • HPS L4 System Bus Group
    • HPS L4 DAP Bus Group
    • HPS L4 System Generic Timestamp Bus
    • SDRAM L3 Interconnect Firewalls
    • Recommended SDRAM Reset Connections
  • Added information to the "NoC Firewalls" table
  • Updated "SDRAM L3 Firewalls" with information about memory region sizes
  • Corrected the "Memory Access Regions for SDRAM Masters" table:
    • Corrected numbers of memory regions
    • Added list of I/O coherent masters
  • Added address map and register description links for the system interconnect.
2017.05.08 Added the following information:
  • Detailed feature list
  • Network connectivity
  • Architecture
  • Firewall and security
  • SDRAM L3 interconnect
  • Arbitration and quality of service
  • Observation network
  • Detailed information about address mappings
  • Master and slave properties
  • Clock and reset
  • Cacheable transaction routing
  • Rate adapter
  • Programming models
2016.10.31 Maintenance release
2016.08.01 Initial beta release
System Interconnect
Table 7.   HPS-FPGA Bridges Revision History
Document Version Changes
2021.06.08 Added "Shareable Domain" information by adding the following sections:
  • F2S Restrictions verses Arm* AMBA* AXI* and ACE-lite* Protocols
  • F2S Example Transactions
  • FPGA-to-SDRAM direct (Cache Non-Allocate)
  • FPGA-to-HPS CCU [Memory (SDRAM/OCRAM) or Peripherals]
  • SDRAM/OCRAM (Cache Non-Allocate)
  • SDRAM/OCRAM (Cache Allocate)
  • Peripherals (Device Non-Bufferable)
2018.05.07 Maintenance release
2017.11.06 Added address map and register description links for the HPS-FPGA bridges.
2017.05.08 Added:
  • Bridges block diagram
  • Expanded "Functional Description of the HPS-to-FPGA Bridge"
  • Explanation of ready latency support
2016.10.28 Maintenance release

2016.08.01

Initial release.

HPS-FPGA Bridges
Table 8.  DMA Controller Revision History

Document Version

Changes

2020.01.25 The following sections were updated:
  • Peripheral Request Interface: Added more information about the Peripheral Request Interface signals.
  • DMA Controller Block Diagram and System Integration: Clarified reset information.
2017.11.06
  • Removed microcoding detail
  • Added S10 Address Map and Register Definitions to the "DMA Controller Address Map" section.
2017.05.08 Added the Programming Model
2016.10.28 Added a top-level system diagram
2016.08.01 Initial release
DMA Controller
Table 9.  On-Chip RAM Revision History

Document Version

Changes

2017.11.06 Added S10 Address Map and Register Definitions to the "On-Chip RAM Address Map and Register Definitions" section.
2017.05.08 Maintenance release
2016.10.28 Added information about exclusive access support

2016.08.01

Initial release

On-Chip RAM
Table 10.  Error Checking and Correction Controller Revision History
Document Version Changes
2017.11.06 Added address map and register description links for the Error Checking and Correction Controller in the Address Map and Register Descriptions section.
2017.05.08 Maintenance release
2016.10.28
  • Added information about sub-word accesses to on-chip RAM in ECC Structure section
  • Added information about the MODSTAT and DECODERSTAT register in the Single-Bit Error Interrupts and Double-bit Error Interrupts sections
  • Added tamper event information in Memory Data Initialization section
2016.08.01 Initial Release
Error Checking and Correction Controller
Table 11.  Clock Manager Revision History
Document Version Changes
2024.01.25

Changed the mpu_ccu_clk signal to mpu_l2_ram_clk in the Hardware Clocks Group figure in Hardware Sequenced Clock Groups.

2018.09.24
  • Corrected the Figure: Clock Manager Block Diagram.
  • Changed the callouts of cb_intosc_hs_div2_clk to cb_intosc__div2_clk.
2017.11.06
  • Added Reset and Security information.
  • Corrected signal names.
  • Added address map and register description links for Clock Manager.
2017.05.08 New sections added:
2016.10.28 Maintenance release
2016.08.01 Initial release
Clock Manager
Table 12.  Reset Manager Revision History
Document Version Changes
2023.10.02 Updated the following sections regarding "Reset Sequences":
  • Warm Reset Sequence
  • Watchdog Reset Sequence
  • Preserving SDRAM Contents
2023.01.27 Added the HPS_COLD_nRESET Pin Function section
2021.02.23 Changed the "self-refresh" information in:
  • Reset Handshaking
  • Warm Reset Sequence
2020.06.19 Reset Manager: Added information to clarify the nCONFIG operation.
2020.01.25 Added a new section: HPS-to-FPGA Reset Sequence.
2019.05.03
  • Updated steps in section: Warm Reset Sequence and Watchdog Reset Sequence.
2018.06.18
  • Added new sections Warm Reset Sequence and Watchdog Reset Sequence.
  • Editorial changes.
2018.05.07
  • Corrected information in the Table: HPS Reset Domains.
  • Corrected the Figure: Reset Manager Block Diagram.
  • Added a new section Modules Under Reset.
  • Removed the Overview, Reset Priority, and Status Register section and merged the content into Functional Description section.
  • Removed the Reset Signals and Registers for Software Deassert section and merged the content into a new Signals and Registers section.
2018.03.02 Added the clarifying footnote for HPS_COLD_RESET and f2s_bridge_rst_n in Table: HPS Reset Domains and section Reset Signals respectively.
2017.11.06
  • Added the following sections:
    • Functional Description
    • Reset Signals
    • Registers for Software Deassert
  • Added address map and register description links for Reset Manager.
2017.05.08 Maintenance release
2016.10.28 Maintenance release
2016.08.01 Initial release
Reset Manager
Table 13.  System Manager Revision History
Document Version Changes
2021.09.28
  • Added information about GPI and GPO (HPS-FPGA gpio) in the System Manager and System Manager Block Diagram.
  • Added the GPIO interconnect between HPS and FPGA section.
2017.11.06
  • Added more information about ECC status and interrupt in the ECC and Parity Control section.
  • Added address map and register description links for System Manager.
2017.05.08 New topic added: Preloader Handoff Information
2016.10.28 Updated figure in the System Manager Block Diagram section.
2016.08.01 Initial release
System Manager
Table 14.  Hard Processor System I/O Pin Multiplexing Revision History

Document Version

Changes

2023.07.17 Updated the drive strength discrete values set in Intel® Stratix® 10 Dedicated Configuration Registers.
2021.09.10 Removed mention of device tree for Platform Designer handoff.
2021.08.04 Updated the link in the Features of the HPS I/O Block section to point to the External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide.
2018.05.07 Maintenance release
2017.11.06
2017.05.08 Maintenance release
2016.10.28 Initial release
Hard Processor System I/O Pin Multiplexing
Table 15.  NAND Flash Controller Revision History

Document Version

Changes

2023.09.19 Added a note regarding boot and performance modes in the Timing Registers chapter.
2023.03.07 Made the following updates:
  • Updated recommended tie-off value for the NAND_ALE and NAND_CLE signals in the NAND Flash Controller Interface Signals (Routed to HPS I/O) table.
  • Updated recommended tie-off value for the nand_ale_o and nand_cle_o signals in the NAND Flash Controller Interface Signals (Routed to FPGA I/O) table.
2022.11.28 Made the following updates:
  • Added complete Signal Interface tables with default and tie off values in section: NAND Flash Controller Signal Description
  • Updated to state that spare area is not ECC protected
2020.01.25 Clarified reset information in section: Taking the NAND Flash Controller Out of Reset.
2017.11.06 Added address map and register description links for NAND Flash Controller.
2017.05.08 Added the Programming Model.
2016.10.28
  • Corrected the block diagram
  • Added content about the clocking architecture
  • Added content about the local memory buffer
  • Added a top-level system diagram
  • Added content about the NAND's interface with the TBU

2016.08.01

Initial release

NAND Flash Controller
Table 16.  SD/MMC Controller Revision History

Document Version

Changes

2024.01.11 Removed the Device Support section.
2022.11.28 Added complete Signal Interface tables with default and tie off values in section: SD/MMC Controller Signal Description
2021.08.04 Added the "SD/MMC Controller Signal Description" table to the SD/MMC Controller Signal Description.
2020.01.25 Clarified reset information in section: Taking the SD/MMC Controller Out of Reset.
2017.11.06 Added address map and register description links for SD/MMC Controller .
2017.05.08 Added the Programming Model.
2016.10.28
  • Added a top-level system diagram
  • Added content about the ETR's interface with the TBU
  • Added a new Memory Requirements section
  • Added content about clocking architecture
  • Removed SPI support in tables in the Features section.

2016.08.01

Initial release

SD/MMC Controller
Table 17.  Ethernet Media Access Controller Revision History
Document Version Changes
2023.01.25 Added link to the Stratix 10 SoC GSRD.
2022.11.28 Added complete Signal Interface tables with default and tie off values in the following sections:
  • EMAC Controller I/O Signals
  • FPGA Routing
  • MDIO Interface
  • Timestamp Interface Controller Signal Description
2022.08.22 Made the following changes:
  • Removed RGMII because it does not support FPGA I/O
2021.04.09 Added emac_clk_tx_i handling requirement for exported HPS EMAC GMII interface in the EMAC FPGA Interface Initialization section.
2020.11.11 Corrected the values for port name emac_phy_txclk_o in Table: PHY Interface Options.
2020.08.18 Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks after bringing the Ethernet PHY out of reset.
2018.03.02 Added the missing step in section EMAC FPGA Interface Initialization.
2017.11.06 Added address map and register description links for Ethernet Media Access Controller.
2017.05.08 Maintenance release
2016.10.28 Maintenance release
2016.08.01 Initial release
Ethernet Media Access Controller
Table 18.  USB 2.0 OTG Controller Revision History
Document Version Changes
2022.11.28 Added complete Signal Interface tables with default and tie off values in section: USB 2.0 ULPI PHY Signal Description
2020.01.25 Clarified reset information in section: Taking the USB 2.0 OTG Controller Out of Reset.
2018.06.18 Removed the erroneous reference of supporting the 4-bit DDR interface.
2017.11.06 Added address map and register description links for USB 2.0 OTG Controller.
2017.05.08 Maintenance release
2016.10.28 Sections added:
2016.08.01 Initial release
USB 2.0 OTG Controller
Table 19.  SPI Controller Revision History
Document Version Changes
2022.11.28 Added complete Signal Interface tables with default and tie off values in sections: Interface to HPS I/O and FPGA Routing
2021.06.08 Removed "Loan I/O" information from SPI Slave
2018.08.08 Removed support for multi-master mode.
2018.03.02 Corrected Figure: SSP Serial Format Continuous Transfer.
2017.11.06 Added address map and register description links for SPI Controller.
2017.05.08 Section added:
  • SPI Programming Model
2016.10.28 Maintenance release
2016.08.01 Initial release
SPI Controller
Table 20.  I2C Controller Revision History
Document Version Changes
2022.11.28 Added complete Signal Interface tables with default and tie off values in section: I2C Controller Signal Description
2019.05.03 Corrected the HPS I2C signal names for FPGA Routing in section: I2C Controller Signal Description.
2017.11.06 Added address map and register description links for I2C Controller.
2017.05.08 Section added:
  • I2C Controller
2016.10.28 Maintenance release
2016.08.01 Initial release
I2C Controller
Table 21.  UART Controller Revision History
Document Version Changes
2022.11.28 Added complete Signal Interface tables with default and tie off values in section: UART Controller Signal Description
2017.11.06 Added address map and register description links for UART Controller.
2017.05.08 Maintenance release
2016.10.28 Maintenance release
2016.08.01 Initial release
UART Controller
Table 22.  General-Purpose I/O Revision History
Document Version Changes
2022.11.28 Added new section: General-Purpose I/O Signal Description containing complete Signal Interface tables with default and tie off values
2017.11.06 Added address map and register description links for General-Purpose I/O Interface.
2017.05.08 Maintenance release
2016.10.28 Maintenance release
2016.08.01 Initial release
General-Purpose I/O Interface
Table 23.  Timers Revision History
Document Version Changes
2017.11.06 Added address map and register description links for Timer.
2017.05.08 Maintenance release
2016.10.28 Maintenance release
2016.08.01 Initial release
Timers
Table 24.  Watchdog Timers Revision History
Document Version Changes
2017.11.06 Added address map and register description links for Watchdog Timers.
2017.05.08 Updated sections:
2016.10.28 Maintenance release
2016.08.01 Initial release
Watchdog Timers
Table 25.  CoreSight Debug and Trace Revision History
Document Version Changes
2017.11.06
  • Added more information about the CoreSight SoC 400 Timestamp Generator
  • Added information for NoC trace ports
  • Added address map and register description links for CoreSight Debug and Trace.
2017.05.08 Added the Programming Model section.
2016.10.28
  • Added a top-level system diagram
  • Added content about the ETR's interface with the TBU

2016.08.01

Initial release

CoreSight Debug and Trace
Table 26.  Booting and Configuration Revision History

Document Version

Changes

2020.11.11 Simplified information in the appendix. For more information, refer to the Intel Stratix 10 Configuration User Guide and Intel Stratix 10 Boot User Guide.
2020.06.30 Added a new section: Device Response to External Configuration and Reset Events to clarify the nCONFIG operation.
2018.12.24
  • Updated the "SDM Pin Mapping" and "Additional Configuration Pin Functions" sections to make the SmartVID feature more clear.
  • In the SDM Pin Mapping table, removed HPS_COLD_nRESET from SDM_IO1 - SDM_IO9 because it is not supported.
  • In the "Reset" section:
    • Removed "Cold Reset and Remote Update" reset type.
    • For the "Power-on-Reset" reset type, corrected the source for the reset from SDM to an external event.
    • Added the "nCONFIG" Reset reset type.
  • Updated the supported flash memory devices and supported SD* card types in the Intel Stratix 10 Configuration Overview topic.
  • Corrected the following statement: Because Intel Stratix 10 devices operate at 1.8 volt and all SD MMC I/Os operate between 2.7 - 3.6 volts, an intermediate voltage level translator is necessary for SD* cards. This statement is only true for SD* cards.
  • Added new Configuration Flow Diagram HPS Configuration First topic.
2018.09.24
  • Modified HPS_COLD_RESET pin naming to HPS_COLD_nRESET pin.
  • Added details about cold reset and remote update to Reset section.
  • Added figure showing pull-ups and pull-downs for theMSEL pins the the MSEL Settings topic.
2018.05.07
  • Removed the Secure Device Manager, Intel Stratix 10 SoC FPGA Bitstream Sections, Booting and Configuration Options sections and subsections and replaced with these rewritten sections:
    • FPGA Configuration First Mode and its subsections
    • HPS Boot First Mode and its subsections
  • Updated SDM Pin Mapping section to include HPS_COLD_RESET pin
  • Removed HPS_WARM_RESET pin function in the Reset and Additional Configuration Pins sections
2017.11.06
  • Added note throughout the chapter that HPS first boot method does not currently support FPGA configuration. This feature is available in a future Intel® Quartus® Prime release.
  • Added design consideration in Configuration and Boot Flash Sources section
  • Added configuration pin setting information for HPS_COLD_RESET and HPS_WARM_RESET pin in Additional Configuration Pin Functions section
  • Moved Backward Compatibility with Intel® Arria® 10 Devices section and subsections to end of appendix
  • Added BSEL pins to table included in the Configuration Pin Compatibility with Intel® Arria® 10 SoC Devices section
  • Added sections:
    • Intel Stratix 10 Bitstream Sections
    • Bitstream in Single Flash Design
    • FPGA Configuration First Single Flash Layout
    • HPS Boot First Single Flash Layout
    • Bitstream in Dual Flash Design
    • FPGA Configuration First Dual Flash Layout
    • HPS Boot First Dual Flash Layout
2017.05.08

Initial release

Booting and Configuration
Table 27.  Accessing the SDM Quad SPI Flash Controller through HPS Revision History
Document Version Changes
2018.06.18 Initial release
Accessing the Secure Device Manager Quad SPI Flash Controller through HPS
Table 28.  Operational Status of the HPS to the FPGA Logic Revision History
Document Version Changes
2024.01.11 Initial release.
Operational Status of the HPS to the FPGA Logic