Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

16.4.2.2.1. Registers Locked Out Pending Command Acceptance

After a command start is issued by setting the start_cmd bit of the cmd register, the following registers cannot be rewritten until the command is accepted by the CIU:
  • Command (cmd)
  • Command argument (cmdarg)
  • Byte count (bytcnt)
  • Block size (blksiz)
  • Clock divider (clkdiv)
  • Clock enable (clkena)
  • Clock source (clksrc)
  • Timeout (tmout)
  • Card type (ctype)

The hardware resets the start_cmd bit after the CIU accepts the command. If a host write to any of these registers is attempted during this locked time, the write is ignored and the hardware lock write error bit (hle) is set to 1 in the raw interrupt status register (rintsts). Additionally, if the interrupt is enabled and not masked for a hardware lock error, an interrupt is sent to the host.

Once a command is accepted, you can send another command to the CIU—which has a one‑deep command queue—under the following conditions:

  • If the previous command is not a data transfer command, the new command is sent to the SD/MMC/CE‑ATA card once the previous command completes.
  • If the previous command is a data transfer command and if the wait previous data complete bit (wait_prvdata_complete) of the cmd register is set to 1 for the new command, the new command is sent to the SD/MMC/CE‑ATA card only when the data transfer completes.
  • If the wait_prvdata_complete bit is 0, the new command is sent to the SD/MMC/CE‑ATA card as soon as the previous command is sent. Typically, use this feature to stop or abort a previous data transfer or query the card status in the middle of a data transfer.