Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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16.4.5. Resets

The SD/MMC controller has one reset signal. The reset manager drives this signal to the SD/MMC controller on a cold or warm reset.
The single reset signal, reset_n, has the following attributes:
  • Active-low
  • Asynchronously asserted and synchronously deasserted to clk (l4_mp_clk)
  • Kept active for at least two clocks of clk or clk_in (whichever has lower frequency)
  • The Phase Shift Logic would also require an appropriate reset synchronized to its clock
  • The resets to each of the two ports are synchronous to different clocks (clk and cclk_in)
Table 145.  Reset Signal Definition
System Reset Source Reset Assertion Deassertion Description
sdmmc_rst_n External reset_n Asynchronous Synchronous—clk (l4_mp_clk) System active-low reset pin. Synchronous to clk.