Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6. System Interconnect

The components of the hard processor system (HPS) communicate with one another, and with other portions of the SoC device, through the system interconnect. The system interconnect consists of the following blocks:

  • The main level 3 (L3) interconnect
  • The SDRAM L3 interconnect
  • The level 4 (L4) buses

The system interconnect is a highly efficient packet-switched network that supports high-throughput traffic. The system interconnect is the main communication bus for the MPU and all hard IP cores in the SoC device.

The system interconnect supports the following features:

  • Configurable ARM® TrustZone* -compliant firewall and security support
  • Multi-tiered bus structure to separate high bandwidth masters from lower bandwidth peripherals and control and status ports
  • Access to an SDRAM hard memory controller in the FPGA fabric
  • Programmable quality-of-service (QoS) optimization
  • On-chip debugging and tracing capabilities

The system interconnect is based on the Arteris® FlexNoC™ network-on-chip (NoC) interconnect technology.