Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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8.3.2. Peripheral Request Interface

The DMAC provides 32 peripheral request interfaces, which can be enabled on an individual basis. The HPS makes eight of these interfaces available to the FPGA, which allows for FPGA soft logic to request a DMA transfer. Two of the eight interfaces are shared by the HPS I2C EMAC2 peripheral under software control. The eight DMAC peripheral request interfaces to the FPGA can be individually enabled using the HPS Platform Designer IP component. For DMA transfers to or from the FPGA, this feature is only necessary if your design requires transfer flow control.

Each FPGA peripheral request interface enabled using the HPS Platform Designer IP component contains the following set of signals exported to the FPGA, where <n> corresponds to a specific request interface enabled in Platform Designer:
  • f2h_dma<n>_req—FPGA peripheral request to the HPS DMAC for a DMA transfer. The DMAC always interprets the f2h_dma<n>_req signal as a burst transaction request, regardless of the level of f2h_dma<n>_single. This is a level-sensitive signal; once asserted by the peripheral, f2h_dma<n>_req must remain asserted until the DMAC asserts f2h_dma<n>_ack. Upon receiving the f2h_dma<n>_ack signal from the DMAC to indicate the burst transaction is complete, the peripheral de-asserts the burst request signal, f2h_dma<n>_req. Once f2h_dma<n>_req is de-asserted by the peripheral, the DMAC de-asserts f2h_dma<n>_ack. If an active level on f2h_dma<n>_req is detected in the Single Transaction Region, then the block is completed using an Early-Terminated Burst Transaction.
  • f2h_dma<n>_ack—HPS DMAC acknowledgment to the FPGA peripheral's request for a DMA transfer. The f2h_dma<n>_ack signal is asserted after the data phase of the last AHB transfer in the current transaction – single or burst – to the peripheral that has completed. For a single transaction, f2h_dma<n>_ack remains asserted until the peripheral de-asserts f2h_dma<n>_single; f2h_dma<n>_ack is de-asserted one hclk cycle later. For a burst transaction, f2h_dma<n>_ack remains asserted until the peripheral de-asserts f2h_dma<n>_req; f2h_dma<n>_ack is de-asserted one hclk cycle later.
  • f2h_dma<n>_single—FPGA peripheral request to the HPS DMAC for a single, non-burst transfer. The f2h_dma<n>_single signal is a status signal that is asserted by a destination peripheral when it can accept at least one destination data item; otherwise it is cleared. For a source peripheral, the f2h_dma<n>_single signal is again a status signal and is asserted by a source peripheral when it can transmit at least one source data item; otherwise it is cleared. Once asserted, f2h_dma<n>_single must remain asserted until f2h_dma<n>_ack is asserted, at which time the peripheral de-asserts f2h_dma<n>_single. This signal is sampled by the DMAC only in the Single Transaction Region of the block transfer. Outside of this region, f2h_dma<n>_single is ignored and all transactions are burst transactions.