Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.5.1.1. Bridge Registers

Each port bridge has a set of corresponding registers in the CCU address map that you can configure.
The following table describes the types of registers you can program to control and view transactions. Register names can have one of two construction:
  • <prefix>_reg_<suffix>
  • <prefix>_reg
<prefix> represents the CCU bridge name. Table 41 lists the possible CCU bridge names. <reg> represents the register function. Table 42 lists the possible <reg> name strings. A <suffix> optionally identifies a specific target slave.
When this chapter discusses the function of a register, the register is represented as *<reg>*. For example, *am_adbase* refers to any base address register. bridge_cpu0_mprt_0_37_am_adbase_mem_ddrreg_sprt_ddrregspace0_0 is an example of a complete register name that represents the am_adbase register for the CPU bridge targeting DDR memory space 0.
Table 42.  Bridge Register Summary
Register <reg> Name Descriptive Name Description
btus Bridge TX Upsizer Status These read-only registers track the status of a bridge transmitter upsizer and downsizer logic.
txid TX Bridge ID This register holds a unique 8-bit identifier for the transmitting portion of a bridge. The txid identifier is the same value as the rxid for a bridge.
btrl Streaming TX Rate Limiter This register exists for each host interface of the transmit bridge for QoS. Configure this register to control the rate of traffic injection from the host into the coherency interconnect.
brs Bridge Receive FIFO Status This register tracks the status of the bridge's receive FIFO from the coherency interconnect.
brus Bridge RX Upsizer Status These read-only registers track the status of a bridge receiver upsizer and downsizer logic.
rxid RX Bridge ID This register holds a unique 8-bit identifier for the receiver portion of a bridge. The rxid identifier is the same value as the txid for a bridge.
am_sts, as_sts Status Flags Register The am_sts register shows the status of the master bridge reads and writes. The as_sts register shows the status of the slave bridge reads and writes.
am_bridge_id, as_bridge_id Bridge ID Register The am_bridge_id and as_bridge_id registers list the unique identifier assigned to the master and slave bridges, respectively.
am_nocver Interconnect Version ID Register This read-only register lists the version of the coherency interconnect.
am_err, as_err Status and Error Register The am_err and as_err registers record the first error event in its corresponding master and slave bridge, respectively.
am_intm, as_intm Interrupt Mask Register You can configure the am_intm and as_intm registers to mask errors recorded in the am_err and as_err registers, respectively.
p_n, where n is a number from 0 to 3 QoS Profile Data This register configures the weight of the bridge QoS.
am_adbase Base Address Register This register specifies a base address for a slave address range that a master can access. Use this register in conjunction with the am_admask register to configure the range. When a master initiates a transaction, an address match occurs when it satisfies the equation: AxADDRS & AM_ADMASK[1]==AM_ADMASE[i]
am_admask Address Mask Register This register specifies a mask value for a slave address range that a master can access. Use this register in conjunction with the am_adbase register to configure the range. When a master initiates a transaction, an address match occurs when it satisfies the equation: AxADDRS & AM_ADMASK[1]==AM_ADMASE[i]
SYSCOREQ_reg Coherency Connect Request Register This register connects a master agent to the CCU system.
SYSCOACK_reg Coherency Connect Request Status Register This read-only register indicates whether a master agent is connected to the CCU system.