Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4. Cache Coherency Unit

The CCU comprises a coherency interconnect, cache coherency controller (CCC), an I/O coherency bridge (IOCB) and support for distributed virtual memory (DVM).

The Intel Stratix 10 Hard Processor System (HPS) cache coherency unit (CCU) ensures consistency of shared data. Dedicated master peripherals in the HPS and those built in FPGA logic access coherent memory through the CCU. Cacheable transactions from the system interconnect route to the CCU.

The CCU provides I/O coherency with the ARM® Cortex® -A53 MPCore™ cache subsystem. I/O coherency, also called one-way coherency, allows HPS peripheral and FPGA masters (I/O masters) to see the same coherent view of system memory as the Cortex® -A53 MPCore™ processor cores, but does not allow the Cortex® -A53 MPCore™ processor cores to be coherent with any caches residing in I/O masters. The CCU also contains error protection logic and logic for optimal performance during coherent accesses. The CCU forwards non-coherent accesses directly to the addressed slave port.

The following master ports interface to the CCU:

  • Cortex® -A53 MPCore™ processor
  • FPGA-to-HPS bridge
  • Translation Control Unit (TCU) (part of the SMMU)
  • HPS peripheral I/O master ports interfacing to the system interconnect:
    • EMAC0/1/2
    • USB0/1
    • DMA
    • SD/MMC
    • NAND
    • Embedded Trace Router (ETR)
The CCU interfaces to the following HPS slave ports:
  • External SDRAM memory
  • On-chip RAM
  • Generic Interrupt Controller (GIC)
  • Peripheral slaves and master CSR slave ports
  • SDRAM register group