Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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14.3.3.5. HPS JTAG Pin MUX Register

Register pinmux_jtag_usefpga selects whether HPS JTAG is accessed from the HPS pins or the FPGA interface. Platform Designer determines the values of the HPS JTAG pin MUX registers automatically when you configure the HPS component.

At cold reset, pinmux_jtag_usefpga defaults to 0 and selects the HPS JTAG access from HPS Pins. A warm reset event does not affect this register.

Note: Although the HPS JTAG Pin MUX Register is configured through the control registers, Intel recommends against reconfiguring this register after I/O configuration is complete.