Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.5.2.6.1. Pipeline Read-Ahead Function

The pipeline read‑ahead function allows for a continuous reading of the flash memory. On receiving a pipeline read command, the flash controller immediately issues a load command to the device. While data is read out with MAP01 commands in a consecutive or multi‑plane address pattern, the flash controller maintains additional cache or multi‑plane read command sequencing for continuous streaming of data from the flash device.

Pipeline read‑ahead commands can read data from the queue in this interleaved fashion. The parameter <PP> denotes the total number of pages in multiples of the number of planes available, and the block address must be plane‑aligned, which keeps the page address constant while incrementing the block address for each page‑size chunk of data. After reading from every plane, the NAND flash controller increments the page address and resets the block address to the initial address. You can also use pipeline write‑ahead commands in multi‑plane mode. The write operation works similarly to the read operation, holding the page address constant while incrementing the block address until all planes are written.

Note: The same four‑entry queue is used to queue the address and page count for pipeline read‑ahead and write‑ahead commands. This commonality requires that you use MAP01 commands to read out all pages for a pipeline read‑ahead command before the next pipeline command can be processed. Similarly, you must write to all pages pertaining to pipeline write‑ahead command before the next pipeline command can be processed.

Because the value of the flag bit of the multiplane_operation register in the config group determines pipeline read‑ahead or write‑ahead behavior, it can only be changed when the pipeline registers are empty.

When the host issues a pipeline read‑ahead command, and the flash controller is idle, the load operation occurs immediately.

Note: The read‑ahead command does not return the data to the host, and the write‑ahead command does not write data to the flash address. The NAND flash controller loads the read data. The read data is returned to the host only when the host issues MAP01 commands to read the data. Similarly, the flash controller loads the write data, and writes it to the flash only when the host issues MAP01 commands to write the data.