Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

5.2.1. System Memory Management Unit Interfaces

The TCU contains the following interfaces:
  • AXI Programming Interface: The Cortex® -A53 MPCore™ configures the SMMU through this interface.
  • ACE-Lite Interface: The TCU uses this interface for page table walk memory requests to the system interconnect.
  • DVM Interface: The Cortex® -A53 MPCore™ uses this interface to send TLB control information to the SMMU TLBs.
  • Interrupt Interface: The TCU sends context and system monitor interrupts to the generic interrupt controller (GIC) through this interface.

Each TBU contains the following interfaces:

  • ACE-Lite Slave Interface: Creates a connection between the I/O device and the SMMU
  • ACE-Lite Master Interface: Creates a connection between the SMMU and the system interconnect
  • Event interface: Generates performance event signals