Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.6.1. LPI Timers

Two timers internal to the EMAC are associated with LPI mode:

  • LPI Link Status (LS) Timer
  • LPI Time Wait (TW) Timer

The LPI LS timer counts, in ms, the time expired since the link status has come up. This timer is cleared every time the link goes down and is incremented when the link is up again and the terminal count as programmed by the software is reached. The PHY interface does not assert the LPI pattern unless the terminal count is reached. This protocol ensures a minimum time for which no LPI pattern is asserted after a link is established with the remote station. This period is defined as one second in the IEEE standard 802.3‑az, version D2.0. The LPI LS timer is 10 bits wide, so the software can program up to 1023 ms.

The LPI TW timer counts, in µs, the time expired since the deassertion of LPI. The terminal count of the timer is the value of resolved transmit TW that is the auto-negotiated time after which the MAC can resume the normal transmit operation. The LPI TW timer is 16 bits wide, so the software can program up to 65535 µs.

The EMAC generates the LPI interrupt when the transmit or receive channel enters or exits the LPI state.