Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.6. Stratix 10 HPS System Interconnect Resets

The diagram below shows the reset domains of the system interconnect along with all the idle handshake signals that control the state of each domain. The driver of each idle handshake signal is also indicated in brackets.

Figure 25. System Interconnect Reset Domains

The majority of the system interconnect (most masters, slaves, datapaths and routers) are reset by l3_rst_n. Almost all transactions in the system interconnect are routed through the l3_rst_n domain. For full functionality of the system interconnect, l3_rst_n must be out of reset.