Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.5.2.1.1. ECC Protection

The CCU coherency directory provides ECC protection. The single-bit error correction and double-bit error detection (SECDED) ECC implementation uses a general Hamming code algorithm. The CCU detects and corrects single-bit errors. The ECC logic in the CCU detects but does not correct double-bit errors.

The data RAM provides 8-bits for ECC. You can program registers to directly access the directory RAM, including the ECC check bits. The hardware supports multiple ways to test ECC logic within the system, including taking an existing directory entry and flipping one or more bits before writing the entry back into the array.

You can disable ECC detection and correction through the ECC Disable Register (agent_ccc0_ccc_ecc_disable) at offset 0x30028 in the CCU.