Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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2.2.6. System Interconnect

The interconnect is a switched, packetized Network-on-Chip (NoC) based on Arteris™ FlexNOC technology. It consists of Network Interface Units (NIUs), datapaths and the service network:
  • NIUs connect to the master and slave interfaces throughout the NoC
  • Datapath switches transport data across the network, from initiator NIUs to target NIUs
  • Service network allows you to update master and slave peripheral security features and access NoC registers

The interconnect is divided into the L3 domain and L4 domain. The L3 interconnect is the high-performance tier of the NoC, used to move high-bandwidth data between masters and slaves in the HPS. The L4 interconnect is a lower-performance tier of the NoC used to connect mid-to-low performance peripherals.

The interconnect is also connected to the Cache Coherency Unit (CCU). The CCU provides additional routing between the MPU, FPGA-to-HPS bridge, L3 interconnect, and SDRAM L3 interconnect.

In addition to providing routing connectivity and arbitration between masters and slaves in the HPS, the NoC features firewall security, QoS mechanisms, and observation probe points throughout the interconnect.