Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.4. Cortex-A53 MPCore System Integration

The Cortex® -A53 MPCore™ is part of the MPU system complex. The system complex is comprised of the Cortex® -A53 MPCore™ , system memory management unit (SMMU), cache coherency unit (CCU), on-chip RAM and generic interrupt controller (GIC). The primary interfaces to the ARM® Cortex® -A53 MPCore™ provide a read and write datapath and support for debug, power management and interrupts.
Figure 4. MPU System Complex and Interfaces
  • Requests from the Cortex® -A53 MPCore™ processor are sent to the cache coherency unit (CCU) by the 128-bit ACE bus master. The CCU supports memory read and write requests and I/O memory-mapped read and write requests. The CCU allows masters to maintain I/O coherency with the Cortex® -A53 MPCore™ subsystem.
  • The System MMU (SMMU) resides outside of the Cortex® -A53 MPCore™ . It consists of a translation control unit (TCU) which controls and manages the address translations of each master's translation buffer unit (TBU). The TLB data of the Cortex® -A53 MPCore™ is managed by the SMMU.
  • The debug access port (DAP) interfaces directly to the processor and can perform invasive or non-invasive debug.
  • The Generic Interrupt Controller (GIC) resides outside of the Cortex® -A53 MPCore™ and sends interrupt requests to the processor through a dedicated bus.