Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.9.1. Clock Structure

The Ethernet Controller has four main clock domains.
  • l4_mp_clk clock
  • EMAC RX clock
  • EMAC TX clock
  • clk_ptp_ref
Figure 88. EMAC Clock Diagram
Figure 89. emac_clkgen Module

Depending on the interface, different clock domains are used:

  • When the DMA master interface is used for EMAC packet transfers, the l4_mp_clk is used as a clock source for both the AXI bus and the CSR register interface. This clock domain is a fully synchronous.
  • The RX and TX FIFO RAMs are driven by the l4_mp_clk.
  • The MDIO interface's clock domain is a derivative of the CSR clock, which comes from l4_mp_clk. Typically MDC clock has a frequency between 1 to 2.5 MHz, however, faster MDC frequencies are supported in this design.
  • The EMAC contains an RX datapath, TX datapath and timestamp interface that all run on separate clock domains.
    • The RX datapath is in the EMAC RX clock domain.
    • The TX datapath is in the EMAC TX clock domain.
    • The timestamp interface is in the clk_ptp_ref clock domain.

The timestamp clock domain provides the capability for EMAC0 to be a timestamp master with internal timestamp enabled and the other two EMACs to be timestamp slaves using the timestamp generated from EMAC0.

The diagram below summarizes the clock domains of the EMAC module:

Figure 90. EMAC Clock Domains

The following table summarizes the clock inputs and outputs to the EMAC.

Table 189.  EMAC Module Clock Inputs and Outputs
Clock Input/Output Frequency Source Description
l4_mp_clk Input 200 MHz Clock Manager

Application clock for DMA bus interface, CSR interface and ECC FIFO RAMs.

clk_ptp_ref Input up to 100 MHz Clock Manager or FPGA fabric This signal is sourced by either the PTP reference clock from the Clock Manager or the FPGA fabric. The source can be selected through the ptp_clk_sel bit of the emac_global register in the System Manager module. When the bit is clear, the emac_ptp_clk is selected and when it is set, the f2h_ptp_ref_clk is selected.
emac*_clk Input Variable depending on divider value of programmed in Clock Manager. Input from Clock Manager This signal is configured in the Clock Manager module and can be enabled to drive the clk_tx_in and clk_rx int signals to the TX and RX clock domains.
clk_tx_i Input Used only in MII mode as a 25 or 2.5 MHz clock source at 100 Mbps and 10 Mbps, respectively. Input from FPGA fabric I/O This signal is used only in MII mode as a TX reference clock.
Note: This clock must be able to perform glitch free switching between 2.5 and 25 MHz.
phy_clk_rx_i Input
  • GMII mode: 125 MHz
  • RGMII mode: 125, 25, or 2.5 MHz
  • MII mode: 25 or 2.5 MHz
  • RMII mode: 50 MHz
This clock input is driven to FPGA or by an HPS I/O input from an external PHY For all modes except, RMII, this clock signal is the RX PHY input clock.

For RMII mode, this input is a 50 MHz reference clock (REF_CLK) from the board or from phy_txclk_o that is divided down automatically to generate the datapath clocks, emac*_clk_rx_i and emac*_clk_tx_i signals. These datapath clocks are 2.5 MHz when operating in 10 Mbps mode and 25 MHz when operating in 100 Mbps mode.

phy_txclk_o Output 125, 50, 25, or 2.5 MHz From internal HPS clk_tx_int to HPS I/O or from FPGA fabric.

This signal is an TX output clock to the PHY.

In RMII mode, this signal can provide the reference clock (50 MHz in 100M /10 Mbps).