Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.2. Cortex-A53 MPCore Processor

The Intel® Stratix® 10 SoC integrates a full-featured ARM® Cortex® -A53 MPCore Processor.

The Cortex® -A53 MPCore™ supports high-performance applications and provides the capability for secure processing and virtualization. Each CPU in the processor has the following features:

  • Support for 32- and 64-bit instruction sets
  • In-order pipeline with symmetric dual-issue of most instructions
  • ARM® NEON* single instruction, multiple data (SIMD) co-processor with a floating-point unit (FPU)
    • Single- and double-precision IEEE-754 floating point math support
    • Integer and polynomial math support
  • Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes
  • ARM® v8 Cryptography Extension
  • Level 1 (L1) cache
    • 32 KB two-way set associative instruction cache
    • Single Error Detect (SED) and parity checking support for L1 instruction cache
    • 32 KB four-way set associative data cache
    • Error checking and correction (ECC), Single Error Correct, Double Error Detect (SECDED) protection for L1 data cache
  • Memory Management Unit (MMU) that communicates with the system MMU (SMMU)
  • Generic timer
  • Governor module that controls clock and reset
  • Debug modules
    • Performance Monitor Unit
    • Embedded Trace Macrocell (ETMv4)
    • CoreSight cross trigger interface

The four CPUs share a 1 MB L2 cache with ECC, SECDED protection. A snoop control unit (SCU) maintains coherency between the CPUs and communicates with the system cache coherency unit (CCU).

At a system level, the Cortex® -A53 MPCore™ interfaces to a generic interrupt controller (GIC), CCU, and system memory management unit (SMMU).