Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.3. FPGA-to-HPS Bridge

The FPGA-to-HPS bridge provides access to the peripherals in the HPS from the FPGA. This access is available to any master implemented in the FPGA fabric. You can configure the bridge slave, which is exposed to the FPGA fabric, to support the ACE-Lite protocol, with a data width of 128 bits.

Table 79.   FPGA-to-HPS Bridge PropertiesThe following table lists the properties of the FPGA-to-HPS bridge, including the configurable slave interface exposed to the FPGA fabric.
Bridge Property Value

Data width9

128 bits

Clock domain

fpga2hps_clk

Address width

40 bits

ID width

4 bits

Read acceptance

8 transactions

Write acceptance

8 transactions

Total acceptance

8 transactions

9 The bridge master data width is user-configurable at the time you instantiate the HPS component in your system.