Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.5.13.1. GIC Block Diagram

The GIC detects private peripheral interrupts (PPIs) and shared peripheral interrupts (SPIs) from interrupt signals. Software-generated interrupts are detected through the register interface.
Figure 6. GIC Block Diagram

Each CPU generates a signal for every private peripheral interrupt ID (PPI ID). There is only one input signal for each SPI interrupt ID shared among the four CPUs. The GIC supports virtual interrupts as well.

The GIC notifies each CPU of an interrupt or virtual interrupt through output signals sent to the Cortex® -A53 MPCore™ .

The configuration and control for the GIC is memory-mapped and accessed through the cache coherency unit (CCU).