Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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3.6.4. Entering Low Power Modes

The Cortex-A53 supports dynamic retention of each core, the L2 cache and the SIMD/floating-point modules. You can configure the amount of time before entering retention through the CPUECTLR and the L2ECTLR registers.

The processor dynamically enters a dormant mode with optional L2 cache retention when not actively executing instructions.