Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

5.1. System Memory Management Unit Features

  • Central TCU that supports five distributed TBUs for the following masters:
    • FPGA
    • DMA
    • EMAC0-2, collectively
    • USB0-1, NAND, SD/MMC, ETR, collectively
    • Secure Device Manager (SDM)
  • Integrates caches for storing page table entries and intermediate table walk data
    • 512-entry macro TLB page table entry cache in the TCU
    • 128-entry micro TLB for table walk data in the FPGA TBU and 32-entry micro TLB for all other distributed TBUs
    • Single-bit error detection and invalidation on error detection for caches
  • Communicates with the MMU of ARM® Cortex® -A53 MPCore™
  • System-wide address translation
  • Address virtualization
  • Support for 32 contexts
  • Allows two stages of translation or combined (stage 1 and stage 2) translation
    • Secure or non-secure translation capability in stage 1
    • Support for modifying attributes from stage 1 to stage 2 translation
    • Capable of multiple levels of address lookup
    • Allows bypassing or disabling stages
  • Supports up to 49-bit virtual addresses and up to 48-bit physical and intermediate physical addresses
  • Provides programmable Quality of Service (QoS) to support page table walk arbitration
  • Provides fault handling, logging and interrupts for translation errors
  • Supports debug