Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

2.2.5.1. HPS-FPGA Memory-Mapped Interfaces

The HPS-FPGA memory-mapped interfaces provide the major communication channels between the FPGA fabric and the HPS. The HPS-FPGA memory-mapped interfaces include:

  • FPGA-to-HPS bridge—a high–performance bus with a fixed data width of 128 bits, allowing the FPGA fabric to master transactions to the slaves in the HPS. This interface allows the FPGA fabric to have full visibility into the HPS address space. This interface supports single-direction I/O coherency with the HPS MPU.
  • HPS-to-FPGA bridge—a high–performance interface with a configurable data width of 32, 64, or 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric.
  • Lightweight HPS-to-FPGA bridge—an interface with a 32–bit fixed data width, allowing the HPS to master transactions to slaves in the FPGA fabric. This bridge is primarily used for control and status register accesses.
  • FPGA-to-SDRAM port—three high–performance AXI-4 interfaces with data widths of 32, 64, or 128 bits, allowing the user-logic in the FPGA to access SDRAM through the HPS SDRAM L3 Interconnect.