Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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5.4.9. System Memory Management Unit Interrupts

Table 55.  SMMU Interrupt Descriptions
Interrupt Type GIC Interrupt Name(s) Description
Global Fault Interrupt

gbl_flt_irpt_s

gbl_flt_irpt_ns

The SMMU asserts the global fault interrupt when a fault is identified in the translation process before a context is mapped. The SMMU provides both a secure (gbl_flt_irpt_s) and non-secure (gbl_flt_irpt_ns) global fault interrupt signal to the generic interrupt controller (GIC).
Performance Monitoring Interrupt

perf_irpt_FPGA_TBU

perf_irpt_DMA_TBU

perf_irpt_EMAC_TBU

perf_irpt_IO_TBU

The SMMU asserts this interrupt when a performance counter overflows.
Combined Interrupt

comb_irpt_ns

comb_irpt_s

The non-secure combined interrupt is the logical OR of glb_flt_irpt_ns, perf_irpt_<tbu_name> and cxt_irpt_<number>

The secure combined interrupt is the logical OR of glb_flt_irpt_s, perf_irpt_<tbu_name> and cxt_irpt_<number>

Context Interrupt cxt_irpt_0 through cxt_irpt_31 The SMMU asserts one of these interrupts when a context fault is detected.
System Monitor Interrupt sys_mon_0 through sys_mon_11 Each TBU has a system monitor interrupt that it can assert when it detects a fault.