Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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11.3.6. Resets

When the POR to the Clock Manager is de-asserted all the other modules in the system are still in reset. This ensures that the Clock Manager is the first module to come out of POR reset. Once the Clock Manager is out of reset, boot_clk is propagated on all the clocks going out from the clock manager.

Therefore, POR is the main reset domain for the clock manager. The Reset Manager also sends POR to the Cortex-A53 MPCore processor.

After a POR reset:
  • All hardware-managed clocks are in Boot Mode and default to the boot_clk (cb_intosc_div2_clk) with all external counters/dividers set to 1 (except for the exceptions).
  • All software-managed clocks may be in Boot Mode, bypassed to boot_clk.
  • Default registers are set to enable state, counters/dividers are set at their minimum value, and all external bypasses are set to boot_clk.

The reset manager brings the clock manager out of cold reset first in order to provide clocks to the rest of the blocks. After POR is de-asserted, clock manager enables boot_clk to the rest of the system before the module resets are de-asserted.

When Reset manager issues a Boot Mode request to clock manager, these steps are followed:
  1. Based on the status of the hps_clk_f fuse during POR, Secure Device Manager (SDM) indicates if the boot clock should be secure.
    1. If secure clocks are enabled, boot_clk transitions gracefully to cb_intosc_div2_clk.
    2. If secure clocks are not enabled, boot_clk transitions gracefully to HPS_OSC_CLK.
    Note: The security fuse is only sampled during cold reset and warm reset. The security fuse HPS CLK allows the user to enable secure clocks. If clearing RAM on a Cold or Warm reset, the user should enable secure clocks (cb_intosc_clk divide by 2).
  2. The Clock Manager gracefully transitions Hardware-Managed and Software Managed clocks into Boot Mode as follows:
    1. Disable all output clocks including Hardware and Software-Managed clocks.
    2. Wait for all clocks to be disabled, and do the following two things:
      1. Bypass all external Hardware and Software-Managed clocks.
      2. Update Hardware-Managed external counters/dividers to Boot Mode settings.
    3. Wait for all bypasses to switch, and then synchronously reset the CSR registers.
    4. Enable all clocks.
  3. After Hardware Managed Clocks have transitioned, the Clock Manager acknowledges the Reset Manager.