Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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19.4.2.1.1. SPI Master Bit-Rate Clock

The maximum frequency of the SPI master bit‑rate clock (sclk_out) is one‑half the frequency of SPI master clock (l4_main_clk). This allows the shift control logic to capture data on one clock edge of sclk_out and propagate data on the opposite edge. The sclk_out line toggles only when an active transfer is in progress. At all other times it is held in an inactive state, as defined by the serial protocol under which it operates. †

Figure 95. Maximum sclk_out/l4_main_clk Ratio

The frequency of sclk_out can be derived from the equation below, where <SPI clock> is l4_main_clk for both master and slave modules. †

Fsclk_out = F<SPI clock> / SCKDV

SCKDV is a bit field in the register BAUDR, holding any even value in the range 2 to 65,534. If SCKDV is 0, then sclk_out is disabled. †

The following equation describes the frequency ratio restrictions between the bit‑rate clock sclk_out and the SPI master peripheral clock. The SPI master peripheral clock must be at least double the offchip master clock. †

Table 200.  SPI Master Peripheral Clock
SPI Master Peripheral Clock

Fl4_main_clk >= 2 x (maximum Fsclk_out) †