Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.1. ECC Controller Features

The features supported by each ECC controller are:

  • Hamming code-based ECC calculations
  • Single-bit error detection and correction
  • Double-bit error detection
  • Dedicated hardware block for memory data initialization
  • Indirect memory access for:
    • Data correction on the corrupted memory address
    • Data and ECC syndrome bit error injection
  • Watchdog timeout for indirect access to prevent bus stall
  • Display of the current single or double-bit error memory address
  • Single-bit error occurrence counter
  • Look-up table (LUT) for logging single-bit error memory address
  • Interrupt generated upon single and double-bit errors
  • User-controllable interrupt assertion for test purposes