Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

16.4.1. SD/MMC/CE-ATA Protocol

The SD/MMC/CE‑ATA protocol is based on command and data bit streams that are initiated by a start bit and terminated by a stop bit. Additionally, the SD/MMC controller provides a reference clock and is the only master interface that can initiate a transaction.
  • Command—a token transmitted serially on the CMD pin that starts an operation.
  • Response—a token from the card transmitted serially on the CMD pin in response to certain commands.
  • Data—transferred serially using the data pins for data movement commands.

In the following figure, the clock is a representative only and does not show the exact number of clock cycles.

Figure 53. Multiple–Block Read Operation

The following figure illustrates an example of a command token sent by the host in a multiple‑block write operation.

Figure 54. Multiple–Block Write Operation