Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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7.3.1. FPGA-to-HPS and FPGA-to-SDRAM Restrictions

Intel® Stratix® 10 uses all of the signaling defined within the ARM® AMBA* AXI* and ACE-Lite* Protocol Specification, except for the AxDOMAIN signaling and AxBURST signaling.

The AxUSER bits are not exposed since there is no need to restrict the masters within each bridge path.