Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

16.4.2.7.2. PBL and Watermark Levels

This table shows legal PBL and FIFO buffer watermark values for internal DMA controller data transfer operations.

Table 134.  PBL and Watermark Levels
PBL (Number of transfers) TX/RX FIFO Buffer Watermark Value

1

greater than or equal to 1

4

greater than or equal to 4

8

greater than or equal to 8

16

greater than or equal to 16

32

greater than or equal to 32

64

greater than or equal to 64

128

greater than or equal to 128

256

greater than or equal to 256