Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.3.3.2. Intel Stratix 10 Dedicated Configuration Registers

Configuration registers for each dedicated I/O pin allow software to control the corresponding I/O cell. These registers, io0ctrl through io47ctrl, allow software to set the following characteristics:

  • Drive strength discrete values set to 2, 4, 6, or 8 mA
  • Slow/Fast Slew rate control
  • Internal weak pullup
  • internal weak pulldown
  • Open drain
  • Schmitt trigger/TTL input

A warm reset event does not affect these registers.

In addition, registers io0_delay through io47_delay allow software to set the delay chains in each of the dedicated I/Os.

Note: Although the dedicated I/O pins are configured through the control registers, Intel recommends against reconfiguring the dedicated I/O pins after I/O configuration is complete.