Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

25.1. Features of CoreSight Debug and Trace

The CoreSight debug and trace system offers the following features:

  • One Debug APB interface slave for debug access
  • Contains the following components for the ARM® Cortex-A53 MPCore™ interface:
    • One Embedded Trace Macrocell (ETM) source per CPU with the ATB slave interface
    • One Cross Trigger Interface (CTI) per CPU
    • One Cross Trigger Matrix (CTM) for four CPU Triggers
  • Supports four Trace input streams from CPUs through ATB buses
  • Supports Trace input stream through AXI slave from the L3 interconnect
  • Supports Trace Replicator for output interfaces
  • Supports two authentication replicators:
    • CoreSight system
    • HPS MPU
  • Supports Trace output bus through I/O pins
  • Supports Trace output bus to the FPGA fabric
  • Supports two trace outputs of NoC ports
    • MPFE NoC trace port—Disabled by default and all of the signals are in an invalid state
    • HPS NoC trace port—Connected to port 5 of the ATB
  • Capability to route trace data to any slave accessible to the Embedded Trace Router (ETR) AXI master connected to the L3 interconnect
  • Capability for the following components to trigger each other through the embedded cross-trigger system:
    • ARM® Cortex® -A53 MPCore™
    • FPGA
    • Cross Trigger Interface (CTI)
    • FPGA-CTI
    • Cross Trigger Matrix (CTM)
  • Supports Debug Access Port (DAP) to allow the host to connect to the debugger through the JTAG
  • Supports System Debug access port (DAPB) through the APB Slave
  • Allows debug access to system resources through the DAP AXI Master Interface to the L4 Main Switch
  • DAP supports the ROM table for the debugger to locate CoreSight components
  • Supports the Debug access master APB output port to the MPU
  • Supports the Timestamp generator for a consistent time value to multiple processors
  • Supports ETR AXI Master from Fixed to Incrementing (Incr)
  • Supports Timestamp replicator, encoder/decoder to CS IPs
  • Supports Trace clock from Clock Manager or FPGA Fabric
  • Supports CS clocks and clock enables (cs_at_clk/cs_pdbg_clk) inputs
  • Supports JTAG TAP controller reset without nTRST pin and software reset bit57
57 The reset occurs by connecting the JTAG system reset (SRST pin) to the HPS reset pin.