Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.1.1.2.5. SDRAM Connections

The three FPGA-to-SDRAM ports connect to the SDRAM Scheduler, which gives FPGA masters the option of direct, non-coherent access to the SDRAM. All other masters have coherent access to the SDRAM through the CCU, including the MPU, FPGA-to-HPS bridge, and HPS peripheral DMA masters.