Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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A.2.1. Boot Flow Overview for HPS Boot First Mode

You can boot the HPS and HPS EMIF I/O first before configuring the FPGA core and periphery. The MSEL[2:0] settings determine the source for booting the HPS. In this mode, any of the I/O allocated to the FPGA remain tri-stated while the HPS is booting. The HPS subsequently configures the FPGA core and periphery excluding the HPS EMIF I/O. Software determines the configuration source for the FPGA core and periphery. In HPS boot first mode, you have the option of configuring the FPGA core during the SSBL stage or when the OS boots.

In the context of HPS Boot First mode, the initial configuration of HPS EMIF I/O and loading of HPS FSBL is called "Phase 1 configuration". The subsequent configuration of FPGA core and periphery by HPS is called "Phase 2 configuration". The Phase 1 and Phase 2 configuration files must be generated from the same Intel® Quartus® Prime Pro Edition software version, this includes patches installed if applicable.

A typical HPS Boot First flow may look like the following figure. You can use U-Boot, Unified Extensible Firmware Interface (UEFI) or a custom boot loader for your FSBL or SSBL. An example of an OS is Linux or an RTOS. The flow includes the time from power-on-reset (TPOR) to boot completion (TBoot_Complete).
Figure 145. Typical HPS Boot First Flow
Table 229.  HPS Boot First Stages
Time Boot Stage Device State
TPOR POR Power-on reset
T1 to T2 SDM- Boot ROM
  1. SDM samples the MSEL pins to determine the configuration scheme and boot source.
  2. SDM establishes the device security level based on eFuse values.
  3. SDM initializes the device by reading the configuration firmware (initial part of the bitstream) from the boot source.
  4. SDM authenticates and decrypts the configuration firmware (this process occurs as necessary throughout the configuration).
  5. SDM starts executing the configuration firmware.
T2 to T3 SDM- Configuration Firmware
  1. SDM configures the HPS EMIF I/O and the rest of the user-configured SDM I/O.
  2. SDM loads the FSBL from the bitstream into HPS on-chip RAM.
  3. SDM enables HPS SDRAM I/O and optionally enables HPS debug.
  4. HPS is released from reset.
T3 to T4 FSBL
  1. The FSBL initializes the HPS, including the SDRAM.
  2. FSBL obtains the SSBL from HPS flash or by requesting flash access from the SDM.
  3. FSBL loads the SSBL into SDRAM.
  4. HPS peripheral I/O pin mux and buffers are configured. Clocks, resets and bridges are also configured.
  5. HPS I/O peripherals are available.
T4 to T5 SSBL
  • HPS bootstrap completes.

After bootstrap completes, any of the following steps may occur:

  1. The FPGA core configuration loads into SDRAM from one of the following sources:
    • SDM flash
    • HPS alternate flash
    • EMAC interface
  2. HPS requests SDM to configure the FPGA core.59
  3. FPGA enters user mode
  4. OS is loaded into SDRAM.
T5 to TBoot_Complete OS
  1. OS boot occurs and applications are scheduled for runtime launch
  2. (Optional step) OS initiates FPGA configuration through a secure monitor call (SMC) to the SSBL, which then initiates the request to the SDM.
Note: The location of the source files for configuration, FSBL, SSBL and OS can vary.
59 FPGA I/O and FPGA core configuration can occur at the SSBL or OS stage, but is typically configured during the SSBL stage.